The invention relates to error correction devices, and in particular to methods for correcting errors by burst read and write, burst write or burst read-modify-write (RMW) operations.
When a data error stored in a dynamic random access memory (DRAM) device is detected, the data is corrected with a read-modify-write (RMW) operation. A conventional RMW operation is applied in such a manner that data is read out using an RMW function of the DRAM. The read data is then modified by an external circuit. The modified data is finally restored in the corresponding memory cell within the DRAM. The conventional RMW operation requires a relatively long processing time defined by the operating cycle of the DRAM, however resulting in inconvenience and performance degradation.
FIG. 1 shows a conventional scheme of an error correction device 1. The error correction device 1 comprises a decoder 10, a memory controller 11, and a dynamic random access memory (DRAM) 12. The DRAM stores a plurality of bytes of data. The error correction device 1 performs an RMW operation as each byte of data stored in the DRAM 12 is modified. The decoder 10 receives error correction codes (ECCs) and decodes a plurality of error values according to the ECCs. FIG. 2 depicts commands of the memory controller 11 in RMW operations, wherein the label “20” represents the commands of the memory controller 11, the label “21” represents reading/writing data on a DRAM bus, and the label “22” represents the error values. Referring FIGS. 1 and 2, one example of the correction of one byte of data D1 will be described. The memory controller 11 sends a pre-charge command (PRE) and an active command (ACT) to the DRAM 12, so that an address of the data D1 to be modified in the DRAM 12 is located. When the memory controller 11 then sends a read command (RD) to the DRAM 12, the DRAM 12 transmits the data D1 to a computing unit 13 in the memory controller 11 through the DRAM bus. The computing unit 13 also receives the error values from the decoder 10. The computing unit 13 performs a logic operation for the data D1 and the corresponding error value E1 to modify the data. When the memory controller 11 sends a write command (WR) to the DRAM 12, the modified data W1 is transmitted to the DRAM 12 from the computing unit 13 and restored in the corresponding address. Therefore, according to the conventional error correction device 1, the memory controller sends n pre-charge commands (PREs), n active commands (ACTs), n read commands, and n write commands for n bytes of data to be modified.
In FIG. 2, the memory controller sends no-operation commands (NOPs) between the pre-charge command (PRE) and the active command (ACT), between the active command (ACT) and the read command (RD), and between the read command (RD) wand the write command (WR). These no-operation commands (NOPs) prevent unwanted commands during idle or wait states. The label “PRMW” represent the duration of one RMW operation. The label “Trp20” represents the delay from the pre-charge command (PRE) to the active command (ACT), the label “Trcd20” represents the delay from the active command (ACT) to the read command (RD), the label “Trcl20” represents the delay from the read command (RD) to the time when the data D1 on the DRAM bus. Referring to FIG. 2, in one RMW operation, the error correction device 1 requires (Trp20+Trcd20+Tcl20+1(NOP 23)+1(WR)) cycles. “NOP23” is inserted to prevent DRAM Bus contention. It is assumed that each of the delays Trp20, Trcd20, and Trcl20 consumes 3 cycles, thus 11 cycles will be consumed when one byte of data is modified. A cluster of a blue-ray disc (BD) has 248*304 bytes, and it is assumed the error rate of a blue-ray disc is 5%. When the error correction device 1 is employed in a blue-ray disc, it will consume about 41459 cycles ((248*304*11*5%)=˜41459). These cycle will degrade the DRAM bandwidth utilization. The following table shows the percentage of error correction cycles for different DISC speed. It is obvious that the percentage is higher when Disc speed is higher. As a result, it is very worthful to reduce the cycle consumed for error correction
Blu-RayDISCCycles for 1 ClusterPercentage of ErrorSpeed(Asuume 1 cycle = 10 ns)correction1×956000 cycles41459/956000 = 4.33%4×239000 cycles41459/239000 = 17.35%8×119500 cycles41459/119500 = 34.69%14×  68286 cycles41459/68286 = 60.71%